The present inventive concept generally relates to the field of electronics and, more particularly, to memory devices.
Memory devices having a high density, a low power consumption and a high operation speed have been developed. High density memory devices may include fine patterns and those fine patterns may cause a loading mismatch between a bit line and a complementary bit line connected to a bit line sense amplifier or a threshold voltage mismatch between transistors in the bit line sense amplifier. These mismatches may decrease sensing efficiency of a bit line sense amplifier by reducing, for example, a sensing margin or a sensing speed.